Towards Chip-on-Chip Neuroscience: Fast Mining of Frequent Episodes Using Graphics Processors
نویسندگان
چکیده
Computational neuroscience is being revolutionized with the advent of multi-electrode arrays that provide real-time, dynamic, perspectives into brain function. Mining event streams from these chips is critical to understanding the firing patterns of neurons and to gaining insight into the underlying cellular activity. We present a GPGPU solution to mining spike trains. We focus on mining frequent episodes which captures coordinated events across time even in the presence of intervening background/“junk” events. Our algorithmic contributions are two-fold: MapConcatenate, a new computationto-core mapping scheme, and a two-pass elimination approach to quickly find supported episodes from a large number of candidates. Together, they help realize a real-time “chip-on-chip” solution to neuroscience data mining, where one chip (the multi-electrode array) supplies the spike train data and another (the GPGPU) mines it at a scale unachievable previously. Evaluation on both synthetic and real datasets demonstrate the potential of our approach.
منابع مشابه
A Fully Integrated Range-Finder Based on the Line-Stripe Method
In this paper, an imaging chip for acquiring range information using by 0.35 μm CMOS technology and 5V power supply has been described. The system can extract range information without any mechanical movement and all the signal processing is done on the chip. All of the image sensors and mixed-signal processors are integrated in the chip. The design range is 1.5m-10m with 18 scales.
متن کاملA Routing-Aware Simulated Annealing-based Placement Method in Wireless Network on Chips
Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links. Using these wireless links makes packets reach destination nodes faster and with less power consumption. These wireless links are provided by wireless interfaces in wireless routers. The WiNoC archite...
متن کاملChip Formation Process using Finite Element Simulation “Influence of Cutting Speed Variation”
The main aim of this paper is to study the material removal phenomenon using the finite element method (FEM) analysis for orthogonal cutting, and the impact of cutting speed variation on the chip formation, stress and plastic deformation. We have explored different constitutive models describing the tool-workpiece interaction. The Johnson-Cook constitutive model with damage initiation and damag...
متن کاملGPGPU-Accelerated Instruction Accurate and Fast Simulation of Thousand-core Platforms
Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, performance (and power) evaluation of these massively parallel architectures. However, architectural simulation performance is a serious concern, as virtual platforms and simulation...
متن کاملCost-aware Topology Customization of Mesh-based Networks-on-Chip
Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- CoRR
دوره abs/0905.2200 شماره
صفحات -
تاریخ انتشار 2009